Texas Instruments 45-nm Chip Manufacturing Process Doubles Output per Wafer, Lowers Power and Boosts Performance

Texas Instruments 45-nm Chip Manufacturing Process Doubles Output per Wafer, Lowers Power and Boosts Performance

June 13, 2006

Consumers to See Improved Video Quality, Longer Battery Life in Portable Devices, More Applications Running Concurrently

    HONOLULU, June 13 /Xinhua-PRNewswire/ -- Before the
start of the prestigious 2006 Symposium on VLSI Technology,
Texas Instruments Incorporated (NYSE: TXN) (TI) unveiled
details of a 45-nanometer (nm) semiconductor manufacturing
process that leverages a "wet" lithography
process to double the number of chips produced on each
silicon wafer, increase processing performance and reduce
power consumption.  Through the use of numerous proprietary
techniques, TI will drive the capabilities of its
multi-million transistor, system-on-chip processors to new
levels, increasing performance by 30 percent while reducing
power consumption 40 percent.

    "TI's strength in chip manufacturing has resulted
in a cost-effective process that will deliver 45-nm
products, like mobile phone processors and DSPs, that
simultaneously address performance, power consumption and
transistor density," said Dr. Hans Stork, senior vice
president and chief technology officer, Texas Instruments.
"This gives our customers early access to faster,
smaller and lower power products and continues TI's track
record of delivering millions of units from high yielding
wafers ahead of the industry."

    TI estimates that its 45-nm process and SoC integration
capabilities will mean consumers will experience 30 percent
better video quality or have the ability to run parallel
applications such as a game with 3-D graphics and sound
effects, or conduct a video conference with email running
simultaneously on a mobile phone.  Other projections show
that TI's 45-nm SoCs will support 40 percent longer video
playback minutes and cell phone stand-by times 30 percent
longer than before.

    Emphasis on Lowering Power, Increasing Integration

    The convergence of communications and computing on
mobile devices, and the growing use of high performance
multimedia, gaming and productivity applications, has
pushed lower power consumption to the forefront of
semiconductor technology advancement.  

    TI's 45-nm process leverages SmartReflex(TM) power and
performance management technologies that combine
intelligent and adaptive silicon, circuit design, and
software to address these power management challenges.  TI
takes a system-level approach with SmartReflex technologies
to extend the capability across an entire 45-nm SoC design,
including adaptive hardware and software technologies that
dynamically control voltage, frequency and power based on
device activity, modes of operation and process and
temperature variation. 
   
    The new TI process also supports the revolutionary
DRP(TM) architecture to integrate digital RF functionality
in single-chip wireless solutions. This SoC approach to
wireless transmit and receive functions, allows TI to apply
its highly efficient CMOS manufacturing infrastructure to
reduce overall system cost, reduce power consumption and
free up board space.  Other integration options in the TI
45-nm design libraries include a host of analog components
such as resistors, inductors and capacitors that allow
further SoC integration of formerly stand-alone functions.

    Techniques Enhancing Performance, Density

    For the first time, TI will implement the use of 193-nm
immersion photo-lithography to accomplish density
improvements that competitors using dry lithography at
45-nm are unable to achieve.  The use of 193nm immersion
tools delivers the higher resolution and corresponding
smaller device features needed to maximize the benefits of
migrating to a new process.  193nm immersion tools work by
placing a thin layer of liquid between the lens and the
wafer to ease the process of transferring smaller circuit
designs.

    The company's work in this area has resulted in the
development of what it believes to be the smallest 45-nm
SRAM memory cells, occupying only 0.24 square microns, up
to 30 percent smaller than other 45-nm memory cells devices
announced to date.  Memory cells are often the first
development vehicle for new manufacturing technologies and
provide valuable data about transistor densities that will
be achieved on complete SoCs.  

    Other improvements in how many transistors TI's 45-nm
process can support on a chip can be attributed to the use
of an ultra low-k dielectric that achieves a k value of
2.5, and reduces interconnect capacitance by 10 percent. 
This will be TI's third-generation process technology to
use low k dielectrics for reducing capacitance and
propagation delays within a device's interconnect layers,
and boosting chip performance.

    Maximizing Design Flexibility, Optimization

    As with its previous generation process technologies,
TI will offer several optimized 45nm recipes to address the
unique requirements of each end product or application. 
Through adjustments to the transistors' gate length,
threshold voltage, gate dielectric thickness or bias
conditions, and others, circuit designers have a several
options for creating flexible, optimized designs.

    TI's low power 45-nm offering will extend battery life
in portable products, while offering the performance to
handle advanced multimedia functionality in a tightly
integrated design.  A mid-range process will support TI
DSPs and TI's high performance ASIC library for
communications infrastructure products.  TI's highest
performance 45-nm option supports MPU-class performance.

    A collection of strain techniques will enhance
transistor performance and minimize leakage for all three
process versions of the process, including TI's first use
of silicon-germanium in its strain application.  Finally,
TI is considering techniques to cost-effectively enhance
performance through use of a dual work function metal gate
at some point in its 45-nm technology roadmap.  Options
include the use of full-silicidation-of-polysilicon (FuSI),
or a combination of metal plus a silicide.  Currently being
explored for the highest performance process, TI believes
leveraging a metal gate with continued use of proven,
silicon nitrided dielectrics delivers the necessary power
consumption control without having to simultaneously move
to new, more complex high-k materials.  

    TI's 45-nm process will be manufactured on 300mm wafers
in the DMOS6 facility in Dallas, Texas.  The low-power ASIC
design library will be available by the end of this year,
with samples of the first SoC product delivered in 2007 and
initial production in mid-2008.

    About Texas Instruments

    Texas Instruments Incorporated provides innovative DSP
and analog technologies to meet our customers' real world
signal processing requirements.  In addition to
Semiconductor, the company includes the Educational &
Productivity Solutions business.  TI is headquartered in
Dallas, Texas, and has manufacturing, design or sales
operations in more than 25 countries.

    Texas Instruments is traded on the New York Stock
Exchange under the symbol TXN. More information is located
on the World Wide Web at http://www.ti.com .

    Trademarks

    SmartReflex and DRP are trademarks of Texas
Instruments.  All other trademarks and registered
trademarks are property of their respective owners.

    For more information, please contact:

     Gary Silcott
     Tel:   [phone]
     Email: [e-mail]

     Tish LeBlanc
     Tel:   [phone]
     Email: [e-mail]

SOURCE  Texas Instruments Incorporated